1. Technical Field
The embodiments described herein relate to a semiconductor integrated circuit and, more particularly, to a semiconductor integrated circuit capable of controlling a test mode.
2. Related Art
Generally, in a semiconductor integrated circuit, faulty analysis and performance of a device are carried out by executing an internal operation test in a test mode. The test mode of the semiconductor integrated circuit can be classified into as either a concurrent test or as a current test. The concurrent test is a simultaneous test in which a plurality of different test modes are executed at the same time in response to various control signals. The current test is a single test mode in which only one test mode is executed in response to the control signals. Accordingly, the concurrent test is preferred because it is capable of simultaneously performing different tests to the semiconductor integrated circuit and therefore a reduction in test time can be realized. To reset the concurrent test, a mode exit has to be achieved appropriately and this mode exit can be made by applying a reset signal using an external signal, e.g., a MRS (Mode Register Set) signal. However in the situation where a specific test mode cannot be executed simultaneously with another different test mode then a current test is needed in which the semiconductor integrated circuit must enter a test mode of the current test after existing a test mode of the concurrent test. As a result, the total test time is increased and this increased total test time can adversely affect the production throughput of the semiconductor integrated circuits.